Information processing device and peripheral devices used therewith

ABSTRACT

An information processing device such as a game machine is selectively connectable to different peripheral devices such as memory devices. The peripheral devices may be provided with characteristics for distinguishing one from another. The information processing device carries out operations based on the peripheral device connected thereto The information processing device may also access memories which store data having different data widths.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application Ser. No.09/863,866, filed May 23, 2001, which is a continuation-in-part ofapplication Ser. No. 09/627,440, filed on Jul. 28, 2000. The contents ofapplication Ser. No. 09/627,440 are incorporated herein by reference.

BACKGROUND AND SUMMARY

[0002] The present application describes, among other things, aninformation processing device which is detachably connectable todifferent types of peripheral devices.

[0003] With reference to FIGS. 21, 22 and 23, a conventional informationprocessing system is described by taking a game system as an example.First, as shown in FIG. 21, a conventional information processing systemCGB includes a program source 100 and a game machine 200. The programsource 100 stores information such as a program necessary for the gamemachine 200 to display images and execute a game, and is structured tobe engageable to the game machine 200 in a detachable manner.

[0004] The program source 100 is preferably in a form of cartridgeincluding a ROM 101, and as required, a RAM 102, a clock 104, and amemory bank controller 105. The ROM 101 is exemplarily implemented bynonvolatile memory typified by read-only memory, flash memory, orEEPROM, and fixedly stores a game program.

[0005] The ROM 101 also stores DOT data of an image representing a gamecharacter, for example, and as required, a program for data exchangeamong other game machines (not shown) and a program for ensuringcompatibility with any program stored in other program sources (notshown) in the conventional image-display game devices. Hereinafter, theprogram source 100 is referred to as a cartridge. FIG. 23 shows an outerappearance of the cartridge 100.

[0006] The RAM 102 is implemented by writable/readable memory typifiedby random-access memory, and has a region for storing temporary datarelevant to the course of the game.

[0007] When a memory chunk of the ROM 101 is too large for a CPU in thegame machine 200, the memory bank controller 105 divides the memorychunk into a plurality of memory banks, and provides those to the ROM101 as an upper address based on bank data provided from the CPU. Thememory bank controller 15 accesses RAM 102 in a similar manner. The ROM101, RAM 102, and memory bank controller 105 are detachably connected tothe game machine 200 via a connector 103.

[0008] The game machine 200 includes an operation key part 202, aCentral Processing Unit (CPU) 203, a connector 204, RAM 205, a displaycontroller 206, a liquid crystal display 207, an interface 208, and aconnector 209. To the CPU 203, the RAM 205 which is working memory fortemporarily storing data for game processing, and the display controller206 are connected. To the display controller 206, the liquid crystaldisplay (LCD) 207 is connected. The CPU 203 is also connected with theconnector 209 via the interface 208. The connector 209 is connected toanother connector 209 provided for other game machine 200 via a cablefor game data exchange with an owner (player) thereof. Here, the CPU 203is connected to the cartridge 100 via the connector 204.

[0009]FIG. 22 shows the outer structure of the information processingsystem CGB. In the information processing system CGB, the connector 204(FIG. 21) provided at the rear of the game machine 200 is engaged withthe connector 103 (FIG. 21) of the cartridge 100 in which the memory islocated. The operation key part 202 is located on the lower part of thesurface (plane) of a housing 201 of the game machine 200. And on theupper part thereof, the liquid crystal display 207 is placed. In thehousing 201, a circuit board having the circuit components as shown inFIG. 21 mounted thereon is accommodated.

[0010] The operation key 202 includes a direction switch 202 a used tomove a cursor or direct any character available for the player indesirable directions, an action switch 202 b used for action command forthe character, a start switch 202 c, and a selection switch 202 d.

[0011] In information processing system CGB, the CPU 203 is an 8-bitCPU. Accordingly, the ROM 101, RAM 102, memory bank controller 105, andconnector 103 are also structured in a data width of 8-bitspecifications. Further, in the information processing system CGB in8-bit specifications, the ROM 101 and RAM 102 are both driven by 5V. Thedata width herein means a signal width for all of a data signal, addresssignal, and control signal exchanged between central processing meanssuch as CPU and memory.

[0012] Even in an information processing system structured like the CGB,the CPU needs to be higher in performance to respond to technologyinnovation in components typified by the CPU, for example, and users'increasing demand for higher processing capability. As a result of suchtechnology innovation, the current CPU differs in number of processingbits from that in the information processing system CGB. As one example,the CPU currently carries out processing in 32-bit, and accordinglymemory system is required to have 32-bit specifications. Under suchcircumstances, the connectors 103 and 204 are preferably also in 32-bitspecifications. Further, as the CPU becomes higher in performance, amemory space available therefor needs to be increased (also increasingthe number of bits of an address signal) in addition to increasing thenumber of processing bits. For example, the number of bits of an addresssignal in the CPU 203 of the conventional information processing systemCGB is 16, while that in the CPU in the new information processingsystem is 24 in some cases. In such case, a memory system needs tocorrespond thereto, and so does a connector, preferably.

[0013] Further, with the advancing semiconductor technology, theinformation processing system of a newly-released type using a cartridgeis generally equipped with an integrated circuit (IC) lower in powerconsumption. As a result, in the new information processing device,semiconductor memory such as ROM and RAM incorporated in the CPU and thecartridge may be driven by different voltage from that for theconventional device. For example, the memory system in the informationprocessing system CGB is driven by 5V, while the new-type informationprocessing system is set to be driven by 3.3 V. Therefore, if acartridge specifically developed for the information processing devicelow in driving voltage is used in the conventional device higher indriving voltage, semiconductor memory in the cartridge suffers due totoo much voltage applied thereto, resulting in memory corruption.

[0014] However, the conventional information processing system CGB hasbeen used by a lot of users over many years, and various programs havebeen developed and supplied to the cartridges 100. The issue here is, asdescribed in the foregoing, in accordance with the new-type CPU higherin performance, the new-type information processing device shall adoptthe bus transfer mode between the CPU and the memory, the connector in32-bit specifications, and the memory system driven by 3.3V. Therefore,this new-type information processing device cannot utilize such programssupplied to the cartridges 100 which are huge software resources so fardeveloped for the conventional information processing system CGB.

[0015] To get around this type of problem, such technique as disclosedin Japanese Patent Laid-Open Publication No. 11-333144 (99-333144) iswell known to keep cartridges compatible with one another. With thistechnology, a monochrome-version cartridge developed for an informationprocessing device with a monochrome display becomes applicable toanother with a color display. As a precondition to realize suchapplication, CPUs in those two information processing devices need to beequal in number of processing bits and the number of bits of an addresssignal. Another precondition is that those two information processingdevices need to be equal in number of connection terminals forconnection with the cartridge, and of bit specifications and the numberof bits of an address signal in each CPU.

[0016] However, if the CPUs in the high- and low-end machines vary inbit specifications and/or number of bits of an address signal, the abovetechnique is not a solution to keep game cartridges compatible with oneanother.

[0017] Recently, in a fixed-type video game machine with a disk drivefor optical recording media such as CD-ROM and DVD, for example, even ifthe recording media differ in type, compatibility has been successfullyretained thereamong.

[0018] However, even in such video game machine successfully retainedcompatibility as such, program data has to be first read from therecording medium, and then transferred to a large-capacity RAM in thevideo game machine for storage. Therefore, this technique is limited inapplicability to the cartridge-type game machine.

[0019] In order to get around such problem, an example informationprocessing device of the present invention (new information processingdevice) is equipped with both an 8-bit CPU for the conventionalinformation processing system CGB and a 32-bit CPU for the new system soas to retain program compatibility (cartridge compatibility)therebetween. With a cartridge for the conventional informationprocessing system CGB inserted, the 8-bit CPU system preferablyoperates, and the 32-bit CPU system operates responding to a gamecartridge for the new information processing device.

[0020] For such preferable operation, there needs to be prepared forthree subjects mentioned below.

[0021] Subject 1) Provide a function of identifying whether memory and aprogram stored in a cartridge are for the new information processingdevice or the information processing system CGB. Then, insert acartridge into the new information processing device so that a voltageappropriate to drive the cartridge is automatically selected before theCPU system of the new information processing device is activated, andthen determine which CPU is appropriate for a program stored in thecartridge. In this manner, there needs to switch a voltage to drive theinserted cartridge before the CPU system corresponding thereto isactivated.

[0022] Subject 2) In order for the new information processing device tobe operable with respect to both types of cartridges for the informationprocessing system CGB and the new information processing device, aconnector which is an external bus needs to be in 8-bit specificationsin accordance with the information processing system CGB. If suchconnector in 8-bit specifications is used for data transfer between acartridge and a corresponding CPU system, the number of bits of a datasignal to be transferred differs, 8 or 32 bits, depending on the type ofcartridge for the information processing system CGB or the newinformation processing device. Further, if the CPU in the newinformation processing device is increased in size of a memory spacecompared with the conventional processing system CGB, the number of bitsof an address signal is increased. Thus, the data width used for datatransfer becomes larger to a greater degree. As such, the bus transfermode should be appropriately switched based on the combination of theCPU and external bus different in data width.

[0023] Subject 3) Further, the cartridge only for the new informationprocessing device needs to be provided with a mechanism to deal with theabove-described difference in data width, that is, a mechanism to dealwith the bus transfer mode in which 32-bit data is transferable via theconnector in 8-bit specifications.

[0024] As to the subject 1, conventionally, such technology has beendisclosed that a slider is moved at the time of connection between an ICcard and a connector, and then an incoming signal to the IC card ischanged (Japanese Patent Laid-Open Publication No. 8-180149 (96-180149);hereinafter, “prior art 1”). Another is a technology of adapter for amemory card (Japanese Patent Laid-Open Publication No. 10-222621(98-222621); hereinafter, “prior art 2”). Therewith, a power-supplyvoltage for a memory card to be inserted is changed depending on whetherthe memory card has a concave part or not.

[0025] Disclosure made in those prior arts 1 and 2 is changing thevoltage or signal supplied to the IC card based on the shape of the ICcard (or memory card) and nothing more than that. Therein, the operationof central processing means corresponding thereto is not disclosed atall.

[0026] As to the subject 2, the conventional information processingdevice, game machine, and the like, are provided with a processor andmemory such as ROM and RAM. The processor and such memory are connectedthrough a bus, and the processor carries out processing to read datastored in the memory or to write data thereinto. The bus is varied intype including a separate bus which is separated into an address bus anda data bus, and a multiplex bus which is obtained by time-sharing acommon bus by address and data (or upper address and lower address, forexample), and these two types of bus specifications are selected basedon the specifications of the processor or memory.

[0027] Herein, a technology of switching the bus between the separatesystem and the multiplex system is disclosed in Japanese PatentLaid-Open Publication No. 5-204820 (93-204820) (hereinafter,“conventional technology 1”) and Japanese Patent Examined PublicationNo. 6-42263 (94-42263) (hereinafter, “conventional technology 2”). Theseconventional technologies enable a single processor to access bothmemory of the separate system (hereinafter, “first memory”) and memoryof the multiplex system (hereinafter, “second memory”).

[0028] However, with such conventional technologies 1 and 2, the numberof bits of a data signal outputted to the first memory (or inputted fromthe first memory) is equal to the number of bits of a data signaloutputted to the second memory (or inputted from the second memory).Therefore, those are not applicable to memories varied in type eachhaving different number of bits of data signal.

[0029] Also with such conventional technologies 1 and 2, the centralprocessing unit determines, based on an address space, whether to accessthe first memory or the second memory. Consequently, those technologiesare applicable only when the central processing unit is connected withthe first and second memories simultaneously and fixedly. Those are notapplicable if the central processing unit is selectively andexchangeably connected, via a connector, with any one memory among thosevaried in type (game cartridge, and the like).

[0030] On the other hand, with the progression of processor technology,processors equipped in information processing devices and game devices,for example, have started to increase in number of bits for dataprocessing (also the number of bits of an address signal). If the numberof bits for data processing is increased in the processors (also, withthe larger number of bits of the address signal), memories correspondingthereto are also required to be wider in data width. In many cases,however, using memories narrower in data width may be rewarding, forexample, cost-wise.

[0031] The information processing devices and game devices, for example,may have several processors varied in number of bits for data processingto ensure the compatibility with software developed in the past.Although the conventional type of game device including severalprocessors is provided with a disk drive for optical recording media, ifmemory cartridges are used therefor, various types of game cartridgeseach corresponding to the processors equipped therein are connected viaa connector. Here, such connector is preferably available for shared useamong those various game cartridges. Therefore, one connector shall beconnectable with memories each having different number of bits of datasignal (also, each different number of bits of an address signal). Inother words, a bus should be available for connecting memories varyingin data width.

[0032] As to the subject 3, there has been a technology of dealing withtwo types of memories differed in the number of bits of an addresssignal, but not yet a technology of dealing with two types of memorieseach having different number of bits of data signal. Needless to say, nodisclosure has been made so far as to memory, in a cartridge having afunction of discriminating whether stored memory and program are for thenew information processing device or the information processing systemCGB.

[0033] In order to get around the above-described subject 1, thisapplication describes an information processing device or a game systemcapable of discriminating between the new and conventional cartridges(program sources), differing in operation mode, for operationappropriate therefor. To realize such information processing device,before a CPU therein accessing memory in a cartridge engaged thereto, adriving voltage to the memory and the operation mode of the CPU are bothchanged depending on the engaged cartridge.

[0034] In order to get around the above-described subject 2, thisapplication also describes an information processing device or a gamesystem capable of discriminating between the new and conventionalcartridges (program sources) differing in operation mode, for operationappropriate therefor. To realize such an information processing device,manners of accessing the cartridges are switched depending on theengaged cartridge. Therefore, the cartridge becomes accessible in eachdifferent manner determined for each type of memory included therein.

[0035] This application further describes an information processingdevice or a game system in which a processor having relatively largenumber of bits for data processing accesses memory having relativelysmall number of bits of data.

[0036] In order to get around the above-described subject 3, thisapplication describes a cartridge (storage device) having a mechanismcorresponding to a multiplex bus transfer mode, which allows datatransfer relatively large in quantity through a connector relativelynarrow in data width. This cartridge is applied to such informationprocessing devices as objected above.

[0037] In one preferable embodiment, in order to clear theabove-described first subject, an information processing devicecomprises a cartridge discriminator, a voltage supplier, and a centralprocessing unit. This structure helps the information processing deviceexecute processing based on data stored in memory whichever provided ina cartridge engaged thereto in a detachable manner. The cartridge is afirst cartridge housing first memory driven by a first voltage or asecond cartridge housing second memory driven by a second voltage. Thefirst cartridge is provided with a marker to be discriminated from thesecond cartridge. Based on the marker, the cartridge discriminatordiscriminates between the first cartridge and the second cartridge. Thevoltage supplier supplies the first voltage when the cartridgediscriminator identifies the engaged cartridge as being the firstcartridge, and supplies the second voltage when identifies as being thesecond cartridge. The central processing unit becomes operational in afirst mode when supplied with the first voltage, and in a second modewith the second voltage. As such, by first identifying the engagedcartridge and then selecting the driving voltage for the memory in thecartridge, the voltage supplied to the memory can be always appropriate.Further, the central processing unit determines its operation modedepending on the selected driving voltage.

[0038] In another preferable embodiment, in order to clear theabove-described second subject, an information processing devicecomprises an external bus having a first width, a cartridgediscriminator, a central processing unit, a first access controller, asecond access controller, and a selector. This structure helps theinformation processing device execute processing based on data stored inmemory whichever provided in a cartridge engaged thereto in a detachablemanner via the external bus. The cartridge is a first cartridge housingfirst memory of a first data width or a second cartridge housing secondmemory of a second data width. The second cartridge is provided with amarker to be discriminated from the first cartridge. Based on themarker, the cartridge discriminator discriminates between the firstcartridge and the second cartridge. The central processing unit accessesthe memory whichever housed in the engaged cartridge. The first accesscontroller controls the external bus under a normal bus control method,and causes the central processing unit to access the first memory. Thesecond access controller controls the external bus under a differentmethod from the one for the first access controller, and causes thecentral processing unit to access the second memory. The selectorselects the first access controller when the cartridge discriminatoridentifies the engaged cartridge as being the first cartridge, andselects said second access controller when identifies as being thesecond cartridge. As such, by identifying the data width of the memorybased on the cartridge housing the memory, the information processingdevice can access the memory in the bus transfer mode appropriatetherefor.

[0039] In still another preferable embodiment, in order to clear theabove-described subject 3, a storage device is provided in a firstcartridge engageable to an information processing device in a detachablemanner, and comprises general-purpose memory for storing data to beexecuted or utilized in the information processing device, and amultiplex bus converter. Here, the information processing device can beengaged with, in a detachable manner, either the first cartridge whereinan internal bus is of a first data width, or a second game cartridgewherein an internal bus is of a second data width narrower than thefirst data width. Further, the information processing device comprises aconnector of the same data width as the second data width, and a centralprocessing unit which accesses the first cartridge in the multiplex bustransfer mode when connected thereto via the connector, and in thenormal bus transfer mode to the second cartridge. The general-purposememory is of the first data width, and stores data which causes thecentral processing unit to execute processing. The multiplex busconverter controls address and data exchange between the centralprocessing unit and the general-purpose memory in a time-sharing manner.As such, data exchange is achieved in a manner corresponding to themultiplex bus transfer mode in the information processing device.

[0040] These and other objects, features, aspects and advantages willbecome more apparent from the following detailed description when takenin conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1 shows external views of an information processing device inassistance of explaining a principle thereof;

[0042]FIG. 2 shows another type of external views of the informationprocessing device of FIG. 1 in assistance of explaining the principlethereof;

[0043]FIG. 3 shows slanted views demonstrating, respectively, a statewhen inserted into a second game machine in the information processingdevice of FIG. 1 is a first and a second game cartridges;

[0044]FIG. 4 shows diagrams in assistance of explaining a cartridgediscrimination method in the information processing device of FIG. 1;

[0045]FIG. 5 shows diagrams in assistance of explaining a cartridgediscrimination method utilizing a photoelectric sensor;

[0046]FIG. 6 is a block diagram showing the system structure of theinformation processing device of FIG. 1;

[0047]FIG. 7 is a block diagram showing main parts relevant to acartridge discrimination function of the information processing deviceof FIG. 6;

[0048]FIG. 8 is a block diagram showing main parts relevant to buscontrol in an 8-bit circuit and a 32-bit circuit shown in FIG. 6;

[0049]FIG. 9 is a slanted view showing the detailed structure of thesecond game cartridge shown in FIG. 1;

[0050]FIG. 10 shows block diagrams each showing the detailed structureof the first and second game cartridges shown in FIG. 6;

[0051]FIG. 11 is a circuit diagram showing connection, to a connector,of ROM in the first game cartridge, and an IC including both ROM and amultiaccess control part in the second game cartridge shown in FIG. 6;

[0052]FIG. 12 is a table in assistance of explaining a cartridgeinterface of the information processing device of FIG. 6;

[0053]FIG. 13 shows memory maps in the first and second game cartridgesshown in FIG. 6;

[0054]FIG. 14 is a block diagram showing the structure of a multiplexconversion circuit;

[0055]FIG. 15 shows time charts in assistance of explaining read/writeaccess operation in the ROM and RAM of the first and second gamecartridges shown in FIG. 6;

[0056]FIG. 16 is a flowchart showing the operation of the informationprocessing device of FIG. 6;

[0057]FIG. 17 is a block diagram showing main parts relevant tocartridge discrimination processing, unlike the example shown in FIG. 7,based on an identification code;

[0058]FIG. 18 is a flowchart showing a cartridge identification methodin the information processing device of FIG. 17;

[0059]FIG. 19 is a block diagram showing main parts relevant to anothercartridge discrimination processing, unlike the examples shown in FIGS.7 and 17, in case of a short being observed;

[0060]FIG. 20 is a flowchart showing a cartridge discrimination methodin the information processing device of FIG. 19;

[0061]FIG. 21 is a block diagram showing the structure of a conventionalinformation processing system CGB;

[0062]FIG. 22 shows an external view of the conventional informationprocessing system CGB shown in FIG. 21; and

[0063]FIG. 23 shows an external view of the cartridge shown in FIG. 21.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0064] By referring to FIGS. 1 to 3, a case is described in which aninformation processing device according to an embodiment of the presentinvention is applied to a game machine (or a game system structured bythis game machine). Specifically, FIGS. 1 and 2 show external views ofsuch game system in assistance of explaining the principle thereof. FIG.3 shows slanted views demonstrating, respectively, a state when insertedinto a second game machine, which is an example of the presentinvention, is a first and a second game cartridges.

[0065] In FIG. 1 and FIG. 3(a), the game system includes a first gamemachine 10 and a second game machine 30. Also included in the gamesystem are a first game cartridge 20 mainly usable for the first gamemachine 10, and a second game cartridge 40 usable for the second gamemachine 30, both usable in a detachable manner. Here, those gamecartridges 20 and 40 are information storage media having a game programstored therein, for example. The first game machine 10 corresponds tothe above-described game machine 200 in FIG. 21, and the first gamecartridge 20 corresponds to the program source 100 in FIG. 21. The firstgame machine 10 is equipped with a CPU with lower performance (e.g.,equivalent in performance to an 8-bit circuit 361 of FIG. 5, which willbe described later), and regarded as a low-end machine with lowerthroughput (conventional type). On the other hand, equipped in thesecond game machine 30 is a CPU with higher performance, and regarded asa high-end machine (new type). Here, the CPU in the second game machine30 is a 16-bit or 32-bit CPU, for example, being higher in throughputthan the first game machine 10. Such CPU is exemplified by a 32-bitcircuit 362 of FIG. 5, which will be also described later. The secondgame machine 30 is additionally provided with another CPU equivalent inperformance to the CPU (8-bit circuit 361 of FIG. 5) in the first gamemachine 10 for compatibility.

[0066] As to the first game cartridge 20, a housing 21 thereof isrectangular or almost square in shape, and its dimensions are a1 high byb1 wide by c1 deep. One plane of the housing 21 is so formed as toinwardly slant at both sides thereof to prevent confusion about whichplane is the top side, and such slanted plane is denoted by a referencenumeral 211. Also, the first game cartridge 20 is internally providedwith a circuit board (not shown) having mounted thereon a semiconductormemory such as ROM 22 with a game program stored therein. This gameprogram is executed by the CPU in the first game machine 10, or the CPU(the 8-bit circuit 361) in the second game machine 30 equivalent inperformance to the CPU in the first game machine 10. Here, in the ROM22, the number of bits of a data signal is 8, that of an address signalis 16, and the driving voltage is 5V. One side surface of the first gamecartridge 20 has an aperture 212, and therefrom, a plurality ofconnection terminals (not shown) formed on one side of such circuitboard is protruding. Here, those connection terminals structure an edgeconnector (not shown).

[0067] As to the first game machine 10, a housing 11 thereof carries aliquid crystal display 12 on the upper part of one plane (same plane asshown in FIG. 1(a)). On the lower part thereof, found are a directionswitch 13 a and an action switch 13 b. On the other plane of the housing11, a concave part 14 is formed on the upper part thereof for cartridgeinsertion. This concave part 14 is in almost the same size as the firstgame cartridge 20 (a1(H)×b1(W)×c1(D)) so as to accept the first gamecartridge 20 therein. Here, the height of the concave part 14 may beshorter than the height a1. Inside the concave part 14, the connector(not shown) is provided for electrical connection among the first gamecartridge 20 and various electrical components such as CPU in the firstgame machine 10. Accordingly, once inserted into the concave part 14,the first game cartridge 20 perfectly fits therein, and the connectionterminals of the first game cartridge 20 are electrically connected tothe connector of the first game machine 10. In this case, the first gamemachine 10 supplies a first driving voltage (e.g., 5V) to the first gamecartridge 20.

[0068] As to the second game cartridge 40, a housing 41 thereof is alsorectangular in shape as is the housing 21 of the first game cartridge20, and its dimensions are a2 high by b1 wide by c1 deep. Here, althoughthe height a2 is shorter (a2<a1) than the housing 21, the width anddepth are the same. As such, by structuring the second game cartridge 40in the same width and depth as the first game cartridge 20, a concavepart 34 of the second game machine 30 can accept both the first andsecond game cartridges 20 and 40. Note here that, the width and depth ofthe first and second game cartridges 20 and 40 are determined accordingto the purpose of the present invention. Similarly to the housing 21 ofthe first game cartridge 20, one plane of the housing 41 is so formed asto inwardly slant at both sides thereof, and such slanted plane isdenoted by a reference numeral 411. Here, as to the second gamecartridge 40, for the purpose of distinguishing from the first gamecartridge 20 by shape, a groove 412 is formed along one side plane, atthe end where abutting the concave part 34 when inserted. The groove 412is an example of a to-be-detected part in the claims. Here, the groove412 may be formed on both side planes of the second game cartridge 40 ifconsidered appropriate in terms of design. The second game cartridge 40also has a protrusion 413 formed, as a stopper when inserted, at one orboth ends of one lateral side, which is not the side inserted into theconcave part 14 of the first game machine 10. Therefore, the lateralside with the protrusion(s) becomes somewhat longer than the other (b2),which is equal in length to the first cartridge 20. The second cartridge40 includes semiconductor memory such as ROM 42 (FIG. 6) having storedtherein a game program to be executed by the 32-bit CPU (the 32-bitcircuit 362) of the second game machine 30, and RAM 43 (FIG. 6) forstoring backup data, and a circuit board 45 (FIG. 9) having mountedthereon various types of integrated circuits (ICs) such as a multiaccesscontrol part 44 (FIG. 6). Here, in the ROM 42, the number of bits of adata signal is 16, that of an address signal is 24, and the drivingvoltage is 3.3V. As to the RAM 43, the number of bits of a data signalis 8, that of an address signal is 16, and the driving voltage is 3.3V.One side surface of the second game cartridge 40, which is the sideinserted into a game machine, has an aperture 414, and therefrom, aplurality of connection terminals (or contacts) 46 (FIG. 9) formed onone side of the circuit board 45 are protruding. Here, those connectionterminals 46 structure an edge connector 47 (FIG. 7).

[0069] As to the second game machine 30, a housing 31 thereof carries aliquid crystal display 32 on the center part of one plane (same plane asshown in FIG. 1(b)). Also, with respect to the liquid crystal display32, a direction switch 33 a is placed on the left and an action switch33 b on the right. On the other plane of the housing 31, the concavepart 34 is formed on the upper part thereof for cartridge insertion.This concave part 34 is in almost the same size as the second gamecartridge 40 (a2(H)×b1(W)×c1(D)) so as to accept the second gamecartridge 40 therein. Here, the height of the concave part 34 may beshorter than the height a2. Inside the concave part 34, a connector 37is provided for electrical connection among the second game cartridge 40and various electrical components such as CPU in the second game machine30. Accordingly, once inserted into the concave part 34, the second gamecartridge 40 perfectly fits therein. In this case, the second gamemachine 30 supplies a second driving voltage (e.g., 3.3V) to the secondgame cartridge 40.

[0070] Next, by referring to FIGS. 2 and 3, assume that the second gamecartridge 40 is inserted into the first game machine 10 and the firstgame cartridge 20 to the second game machine 30.

[0071] As shown in FIG. 2(a), if the second game cartridge 40 isinserted into the first game machine 10, the connection terminals 46 ofthe second game cartridge 40 do not reach the connector of the firstgame machine 10, and thus no appropriate connection is established. Thisis because the height a2 of the second game cartridge 40 is not longenough as the height a1 for the connector of the first game machine 10.Also, the protrusion 413 works as a stopper with respect to the lateralside of the concave part 14. Accordingly, no power-supply voltage issupplied from the first game machine 10 to various IC componentsincluding the semiconductor memory in the second game cartridge 40 viathe connection terminals 46. Thus, those IC components are successfullyprotected from corruption often caused by overvoltage.

[0072] On the other hand, as shown in FIGS. 2(b) and 3(b), described nowis the case that the first game cartridge 20 is inserted into the secondgame machine 30. In this case, as the height a1 of the first gamecartridge 20 is longer than the height a2 of the concave part 34(a2<a1), the connection terminals of the first game cartridge 20 reachthe connector 37 of the second game machine 30, and thus electricalconnection is established. Here, as is a2<a1, the first game cartridge20 does not perfectly fit in the concave part 34, and thus is leftvisible by the difference of a1-a2. At this time, the driving voltagesupplied from the second game machine 30 to the first game cartridge 20is the first driving voltage (5V) instead of the second (e.g., 3.3V).

[0073] As is known from the above, the first game cartridge 20 is usableto both the first and second game machines 10 and 30, and thuscompatibility with the high-end machine is successfully achieved. As tothe second game cartridge 40 usable only to the second game machine 30,even if erroneously inserted into the first game machine 10, noelectrical connection is established. The semiconductor memory, forexample, in the cartridge thus can be protected from corruption oftencaused by overvoltage.

[0074] In this example, the driving voltage for the second gamecartridge 40 is lower than that for the first game cartridge 20. This isbecause the second game cartridge 40 is equipped with electricalcomponents of types driven by lower voltage to reduce power consumption.If there is no need to reduce power consumption, the power-supplyvoltage to both game machines may be in the same level. If so, thesecond game machine 30 has no more need to change the voltage leveldepending on which cartridge is now engaged to itself.

[0075] With reference to FIG. 4, described next is a method how todiscriminate between the first and second game cartridges 20 and 40.Here, the method demonstrated in FIG. 4 utilizes a cartridge shapedetection switch (hereinafter, referred to simply as “detection switch”)35 to detect any difference in shape. Such method is described in detailbelow.

[0076] The detection switch 35 is exemplified by a selector switch, andplaced in the vicinity of the connector 37. The detection switch 35 isselectively connected with either a 3.3V output terminal or a 5V outputterminal provided in a DC-DC converter 383 (FIG. 6). With suchstructure, thus selected power-supply voltage is supplied to apower-supply terminal of the cartridge currently engaged to theconnector 37. In the initial state, the detection switch 35 isstructured to be connected to the 3.3V output terminal.

[0077]FIG. 4(a) shows, views from side, before and after the second gamecartridge 40 is inserted into the concave part 34 of the second gamemachine 30. In this example, the detection switch 35 is placed in thevicinity of a side end part of the concave part 34. Therefore, even ifthe second game cartridge 40 is inserted into the concave part 34, thedetection switch 35 is prevented from abutting the second game cartridge40 due to the groove 412. In such structure, the detection switch 35remains in the initial state, and thus the second game machine 30detects the cartridge as being the second game cartridge 40, andsupplies the voltage of 3.3V therefor.

[0078]FIG. 4(b) shows, views from side, before and after the first gamecartridge 20 is inserted into the concave part 34 of the second gamemachine 30. Unlike the second game cartridge 40, the housing 21 of thefirst game cartridge 20 has no groove 412 formed. Therefore, thedetection switch 35 is pushed down by an end part of the housing 21, andthus the second game machine 30 detects the cartridge as being the firstgame cartridge 20. The voltage of 5V is thus supplied to the first gamecartridge 20.

[0079] Here, described above is the case of the second game cartridge 40having the groove 412. This is not restrictive, and the first gamecartridge 20 may be the one provided with the groove. Also, instead ofthe groove, a protrusion may be provided in a position where abuttingthe detection switch 35. If these are the cases, the detection switch 35should be in the initial position connected to the 5V output terminal.Also, the processing is carried out in a different manner from that forthe example of FIG. 4.

[0080] In this example, cartridge discrimination by shape between thefirst and second cartridges 20 and 40 is done by mechanically contactingthe detection switch 35 to the currently engaged cartridge.Alternatively, cartridge discrimination can be done without contactingthe detection switch 35 to the cartridge. Such non-contacting cartridgediscrimination is carried out exemplarily in a photoelectric sensorsystem and a read switch system.

[0081] FIGS. 5(a) and 5(b) exemplarily show the photoelectric sensorsystem, which is an exemplary transmission-type for identifying thecartridge based on whether light L is transmissible or not. In FIGS.5(a) and 5(b), detection switches 35′ and 35″ both include alight-emitting unit 35 a and an optical sensor 35 b. In FIG. 5(a), a rib35 s′ having an aperture 418′ is additionally included. In FIG. 5(b), arib 35 s″ having no aperture is included instead of the rib 35 s′. Suchstructured rib 35 s′ or rib 35 s″ is provided in the first and secondgame cartridges 20 and 40, while the light-emitting unit 35 a and theoptical sensor 35 b are provided in the concave part 34. Accordingly,the cartridge can be identified based on whether the light L istransmitted or not.

[0082] The photoelectric sensor system shown in FIGS. 5(c) and 5(d) isan exemplary reflection-type for identifying the cartridge based onwhether the light L is reflectable or not. Here, in FIGS. 5(c) and 5(d),detection switches 35′ and 35″ both include a light emitting/receivingunit 35 ab. In FIG. 5(c), the rib 35 s′ as above is also included, andin FIG. 5(d), included is a rib 35 r which is similar to the rib 35 s″but additionally has a reflection plane 419 reflecting the light L. Suchstructured rib 35 s′ or rib 35 r is provided in the first and secondgame cartridges 20 and 40, and the light emitting/receiving unit 35 abare provided in the concave part 34. Accordingly, the cartridge can beidentified based on whether the light L is reflected or not.

[0083] Other than the above, cartridge discrimination between the firstand second game cartridges 20 and 40 can be done in the read switchsystem. In the system, a magnetic substance provided to the cartridgedrives a selector 35 s (FIG. 7) of the detection switch 35 provided inthe concave part 34.

[0084] Next, by referring to FIG. 6, the system block of the game systemand game cartridge according to the embodiment of the present inventionis roughly described. Here, FIG. 6 is a block diagram showing the gamesystem and game cartridge.

[0085] In FIG. 6, the information processing system includes the firstand second game cartridges 20 and 40, and the second game machine 30.The first and second game cartridges 20 and 40 each store informationsuch as program necessary for the second game machine 30 to displayimages and execute a game, and structured to be engageable to the secondgame machine 30 in a detachable manner as described above.

[0086] The second game machine 30 includes the liquid crystal display(LCD) 32, the connector 37, a central processing unit (CPU) 360, and apower-supply unit 380. The CPU 360 includes both the 8-bit circuit 361and the 32-bit circuit 362, and is a unit of a dual processor type. The8-bit circuit 361 is equivalent in performance to the CPU (not shown)equipped in the first game machine 10, which is a low-end machine withlower throughput carrying out 8-bit operation. As to the 32-bit circuit362, its performance is high and unique to the second game machine 30,and carries out 32-bit operation, for example. To the 8-bit and 32-bitcircuits 361 and 362, through buses, connected are an I/O buffercontroller 363, video RAM (V-RAM) 364, working RAM (W-RAM) 365, an LCDcontroller 367, and peripheral circuits 368. The peripheral circuits 368perform sound processing, DMA (direct memory access), timer control,input/output control, and the like.

[0087] To the CPU 360, connected are the liquid crystal display 32, thepower-supply unit 380, an operation key 33, a sound amplifier 391, and aspeaker 392. The power-supply unit 380 includes a power supply 381, apower-supply switch 382, the DC-DC converter 383, and a voltagedetection IC 384. The power supply 381 is preferably a battery, andsupplies power to the DC-DC converter 383 via the power-supply switch382. The DC-DC converter 383 performs voltage transform to thedirect-current power provided by the power-supply 381, and generatesdirect voltages varied in level (e.g., −15V, 2.5V, 3.3V, 5V, and 13.6V).Responding to the user's (or the player's) operation on the operationkey 33, the CPU 360 executes the program stored in the ROM 22 or 42equipped in the first or second game cartridge 20 or 40. Thus, based onthe result obtained thereby, a game image is displayed on the LCD 32,and sound (or sound effects) corresponding to the game image isoutputted from the speaker 392.

[0088] The CPU 360 is also connected with the connector 37 in theconcave part 34. In relation to the position of the connector 37, thedetection switch 35 exemplified by a selector-type microswitch isprovided. As already described, the detection switch 35 detects which ofthe first and second game cartridges 20 and 40 is inserted into theconcave part 34, that is, engaged with the second game machine 30.Specifically, the detection switch 35 detects whether the insertedcartridge has the groove 412 or not. If the groove 412 is detected, thedetection switch 35 determines that the inserted cartridge as being thesecond game cartridge 40, otherwise determines as being the first gamecartridge 20. If detected is the second game cartridge 40, the detectionswitch 35 selects the power-supply voltage of 3.3V for supply thereto.On the other hand, if detected is the first game cartridge 20, selectedis the power-supply voltage of 5V. The CPU 360 also includes a switchingcircuit 369, which activates either the 8-bit circuit 361 or the 32-bitcircuit 362 in response to the output from the detection switch 35.

[0089]FIG. 7 is a block diagram showing parts mainly used todiscriminate between the first and second game cartridges 20 and 40 inthe second game machine 30 shown in FIG. 6. Specifically, in the secondgame cartridge 40, the ROM 42 and RAM 43 structure a 3.3V interfacememory. The 3.3V interface memory enables data transfer in the multiplexmode (details are left for later description). In the first gamecartridge 20, the ROM 22 is a 5V interface memory.

[0090] The CPU 360 includes the switching circuit 369, which selectivelyactivates either the 32-bit circuit 362 or the 8-bit circuit 361 inresponse to a value of a register 362 f provided by the voltagedetection IC 384. In more detail, the 32-bit circuit 362 includes asecond boot ROM 362 e, a second CPU core 362 a, the register 362 f, anda multiplex/8-bit bus controller 362 b. Here, the term “second” denotesthe 32-bit operation unique to the second game machine 30.

[0091] The 8-bit circuit 361 includes a first boot ROM 361 c, a firstCPU core 361 a, and an 8-bit bus controller 361 b. Here. the term“first” denotes the 8-bit operation unique to the first game machine 10.

[0092] A reset circuit 385 resets the CPU 360.

[0093] The detection switch 35 includes the selector 35 s which isselectively connected with either the 3.3V output terminal or the 5Voutput terminal in the DC-DC converter 383 so that the voltage from thusselected output terminal goes to the cartridge inserted into the concavepart 34. Note that, in this example, the selector 35 s is located at the3.3V output terminal when no cartridge is in the concave part 34. Thatis, in the second game machine 30, 3.3V is the reference driving voltagein the memory system.

[0094] In this example, described next is a method of uniquelydetermining an output voltage based on the cartridge type (the first orsecond game cartridge 20 or 40). As described in the foregoing, thedetection switch 35 is placed in a part where the first game cartridge20 partially abuts the selector 35 s when inserted into the concave part34.

[0095] With such structure, the selector 35 s is pushed toward the 5Voutput terminal side as the first game cartridge 20 is coming into theconcave part 34. Thus, the selector 35 s is not connected with the 3.3Voutput terminal in the initial position any more, but is securelyconnected with the 5V output terminal and then retained at the otherpossible position. With the selector 35 s being connected to the 5Voutput terminal, the first game cartridge 20 is electrically connectedto the connector 37, and then is supplied with the DC output of 5V fromthe DC-DC converter 383.

[0096] As described above, the second game cartridge 40 is so shaped asnot to abut the selector 35 s on the way coming into the concave part34. Thus, after the second game cartridge 40 is completely inserted intothe concave part 34, the selector 35 s remains biased and connected tothe 3.3V output terminal. As a result, the second game cartridge 40 issupplied with the DC output of 3.3V from the DC-DC converter 383.

[0097]FIG. 8 is a block diagram showing the detailed structures of the8-bit circuit 361 and the 32-bit circuit 362 shown in FIG. 7. In FIG. 8,the 8-bit circuit 361 includes the first CPU core 361 a, the firstaccess control part (8-bit bus controller) 361 b, and the first boot ROM361 c. The first CPU core 361 a processes an activation program storedin the first boot ROM 361 c, and also carries out game processing basedon a program for the first game machine 10 stored in the ROM 22 in thefirst game cartridge 20. The first CPU core 361 a accesses the ROM 22via the access control part 361 b.

[0098] The 32-bit circuit 362 includes the second CPU core 362 a, thesecond access control part (or multiplex/8-bit bus controller) 362 b,and the second boot ROM 362 e. In more detail, the access control part362 b includes a multiplex bus controller 362 c, and an 8-bit buscontroller 362 d. The second CPU core 362 a processes an activationprogram stored in the boot ROM 362 e, and also carries out gameprocessing based on a program for the second game machine 30 stored inthe ROM 42 in the second game cartridge 40. The second CPU core 362 aaccesses the ROM 42 and RAM 43 in the second game cartridge 40 via theaccess control part 362 b. In more detail, when controlling the ROM 42for reading, the multiplex bus controller 362 c provides, with a firsttiming to the ROM 42, address data A0 to A23 for accessing the ROM 42,and receives data D0 to D15 with a second timing. Accordingly, a busline is partially shared when providing and receiving data. The 8-bitbus controller 362 d performs, when controlling the RAM 43 for datawriting or reading, access control in the similar manner to the 8-bitCPU. Depending on which of the ROM 42 and the RAM 43 is accessed by theCPU, selection is made between the multiplex bus controller 362 c andthe 8-bit bus controller 362 d (specifically, as will be laterdescribed, this selection is made according to the memory space assessedby the CPU).

[0099] Referring to FIG. 9, described next is the internal structure ofthe second game cartridge 40. Here, FIG. 9 is a slanted view showing thedetailed structure of the second game cartridge 40. In FIG. 9, thehousing 41 of the second game cartridge 40 includes an upper housing 41a and a lower housing 41 b. The lower housing 41 b has walls on bothside planes and an upper side, and the inner side of the walls on theside planes each have a concave part 415. In the vicinity of the concavepart 415 and on the inside plane of the lower housing 41 b, a protrusion416 is formed for positioning the circuit board 45. Another protrusion417 (two, in the drawing) is formed on the inner side of the wall on theupper side. The upper housing 41 a has still another protrusion (notshown; as many as the protrusion 417) in a position opposing theprotrusion 417. The protrusion formed on the upper housing 41 a isengaged in between the protrusion 417 and the side wall of the lowerhousing 41 b. Consequently, the upper and lower housings 41 a and 41 bcan be held in position with limited lateral movement. The upper housing41 a also has ribs each formed in a part opposing to the side walls ofthe lower housing 41 b for engagement therewith. Further, the upperhousing 41 a has a convex part 418 in a part opposing to each concave415.

[0100] On the circuit board 45, a one-chip IC 48 including the ROM 42and the multiaccess control part 44 is mounted, and as required, the RAM43 and a backup battery 46 are also mounted. On the circuit board 45,the ROM 42, RAM 43, and battery 46 are connected as appropriate in adesired circuit pattern for electrical connection between thosecomponents and externals. The outer edge of the circuit board 45 hasnotches 451 for engagement with the protrusions 416. On the lower endpart of the circuit board 45, a plurality of connection terminals 46(46-1 to 46-32) are aligned with predetermined intervals. Thoseconnection terminals 46-1 to 46-32 are exposed via the aperture 414 ofthe housing 41, and connected to the connector 37 of the second gamemachine 30. Accordingly, those connection terminals 46-1 to 46-32 formedon the lower side of the circuit board 45 form an edge connector 47.Here, the edge connector 47 is in the same structure as that in thefirst game cartridge 20. Here, the “structure” means the shape of thelower side of the circuit board 45, and alignment, interval between anytwo, and the number of the connection terminals.

[0101] In this embodiment, the ROM 42 and the multiaccess control part44 are in the one-chip IC. This is not restrictive, and the multiaccesscontrol part 44 may be separately provided and wired to the ROM 42. Thisstructure is advantageously easy to manufacture. Also, the ROMs 42 and22 may be non-rewritable mask ROM, rewritable flash ROM, or the like.

[0102] Next, by referring to FIGS. 10 and 11, the detailed functionalstructures of the first and second game cartridges 20 and 40 aredescribed. Here, FIG. 10 shows block diagrams showing the detailedstructures of the first and second game cartridges 20 and 40, and FIG.11 is a circuit diagram showing connection, to the connector 47, of ROM22 in the first game cartridge 20, and the IC 48 including both ROM 42and the multiaccess control part 44 in the second game cartridge 40. Asshown in FIGS. 10(a) and 11(a), the ROM 22 is provided with a pluralityof lead terminals. These lead terminals include, for example, addressterminals A0 to A15 connected to the 16-bit address bus, data terminalsD0 to D7 connected to the 8-bit data bus, control signal terminals (/WR:write bar, /RD: read bar, /CS: chip select bar), and power-supplyterminals (VDD), and connected to the connection terminals 46-1 to46-32. The IC 48 in the second game cartridge 40 carries the ROM 42 andthe multiaccess control part 44 in one chip, and also has a plurality oflead terminals. The lead terminals of the IC 48 include, for example,terminals A0/D0 to A15/D15 in charge of lower 16-bit address data of24-bit address data and 16-bit data (multiplex system), terminals A16 toA23 for upper 8-bit address data of the 24-bit address data, controlsignal terminals (/WR, /RD, /CS, and /CS2), a power-supply terminal(VDD), and the like. Here, the terminals A0/D0 to A15/D15 are used withthe connection terminals (46-6 to 46-21; 6 to 21 are terminal numbersshown in FIG. 12) between first and second timings (multiplex system).

[0103] As shown in FIG. 10(b), in the second game cartridge 40, the /CSsignal is connected to the IC 48 (ROM 42), while the /CS2 signal to theRAM 43. That is, when the /CS signal is outputted, the IC 48 (ROM 42) isactivated, and the RAM 43 is activated in response to the /CS2 signal.Here, the /CS and /CS2 signals are outputted to the access control part362 b based on the address data from the second CPU core 362 a (as willbe described later).

[0104] By referring to FIG. 12, the cartridge interface of the first andsecond game cartridges 20 and 40 is now described. Here, FIG. 12 is atable showing the relationship between the first and second gamecartridges 20 and 40 in view of applications and functions of theterminals. In FIG. 12, the “NO.” column on the left side indicates theterminal number (1 to 32) of the connection terminals 46. The “ROM 22”column indicates terminal functions when the ROM 22 in the first gamecartridge 20 is the one to be accessed. The “ROM 42” column indicatesterminal functions when the ROM 42 in the second game cartridge 40 isthe one to be accessed, and the “RAM 43” column indicates terminalfunctions when the RAM 43 is the one to be accessed. The table showsthat the connection terminals 46-1 to 46-29, and 46-32 are used toaccess both the ROM 22 and RAM 43. Among those connection terminals usedto access the ROM 42, the connection terminals 46-6 to 46-29 are used asthe address terminals A0 to A23 (i.e., terminals A16 to A23 are upperaddresses) with the first timing, and with the second timing, as thedata terminals D0 to D15. The connection terminals 46-6 to 46-21 work asthe address line with the first timing, and as the data line with thesecond timing. Thus, some of the connection terminals work as two typesof signal lines varying in functions (multiplex system). In the below,the connection terminals 46-6 to 46-21 are denoted as AD0 to AD15 todistinguish from those 46-22 to 46-29 which are used as only the addressbus.

[0105] Here, with the second game cartridge 40 engaged, the 32-bitcircuit 362 is activated in the second game machine 30, wherein thenumber of bits of a data signal is 32. On the other hand, as describedin the foregoing, the terminal for the data signal of the cartridgeinterface is 16 bits. Thus, the data is to be inputted/outputted twicein unit of 16-bit.

[0106] By referring to FIG. 13, described next is a memory space in thesecond game machine 30. Here, FIG. 13(a) is a memory map showing amemory space of the 32-bit circuit 362, while FIG. 13(b) is a memory mapshowing a memory space of the 8-bit circuit 361. As shown in FIG. 13(a),addresses from 00000000h to 08000000h are a memory space assigned forinternal ROM, internal RAM, an I/O, a register, and the like, in the32-bit circuit 362, addresses from 08000000h to 0E000000h is a memoryspace for the ROM 42, and addresses from 0E000000h to 0E00FFFFh is amemory space for the RAM 43.

[0107] When the second game machine 30 accesses the second gamecartridge 40, switching processing between the ROM 42 and the RAM 43 iscarried out as below. First, if the second CPU core 362 a outputs theaddresses in the range of 08000000h to 0E000000h, the access controlpart 362 b outputs the /CS signal, and thus the ROM 42 is activated. Onthe other hand, when the second CPU core 362 a outputs the addresses inthe range of 0E000000h to 0E00FFFFh, outputted is the /CS2 signal andthus the RAM 43 is activated.

[0108] As shown in FIG. 13(b), in the 8-bit circuit 361, addresses from0000h to 8000h is a memory space reserved for internal ROM, internalRAM, an I/O, a register, and the like, in the 8-bit circuit 361, andaddresses from 8000h to FFFFh is a memory space for the ROM 22.

[0109] Next, by referring to FIG. 14, described is multiplex conversionutilizing an address counter which enables the sequential access. FIG.14 is a block diagram showing the structure of the multiaccess controlpart 44 in the second game cartridge 40 for realizing access under theabove described multiplex system. In FIG. 14, the multiaccess controlpart 44 is structured by a multiplex conversion circuit including theaddress counter 441 so that the sequential access and random access areappropriately switched. This address counter 441 is a 24-bit counter,and capable of retaining and incrementing the address data. As toinput/output terminals of the multiaccess control part 44, A[23:16] tobe inputted into the address counter 441 means the upper address A23 toA16, and AD[15:0] means either the lower address A15 to A0 or the databus D15 to D0 depending on the timing. Further, to a LOAD terminal ofthe address counter 441, the /CS signal (chip select bar; “/” denotes asbeing low active) is inputted, and to a CLOCK terminal, the /RD signal(read bar) is inputted. Based on these four inputs, the address counter441 outputs a memory address bus MA [23:0] signal for accessing the ROM42. Also, a data bus MD [15:0] connected to the bus line of the ROM 42is connected to AD[15:0] of the terminals 46-6 to 46-21, and then thedata D15 to D0 is outputted.

[0110] By referring to FIG. 15, described next is read/write access ofthe ROM 42, RAM 43, and ROM 22. FIG. 15 shows timing charts for theread/write access of the second game machine 30 to the memory (ROM 22)of the first game cartridge 20 and the memory (ROM 42 and RAM 43) of thesecond game cartridge 40. Specifically, FIG. 15(a) shows the read accessto the ROM 42, FIG. 15(b) the write access to the RAM 43, FIG. 15(c) theread access to the RAM 43, and FIG. 15(d) the read access to the ROM 22.As to the time chart for the read access of the first game machine 10 tothe ROM 22, refer to FIG. 15(d).

[0111] In FIG. 15(a), from top to bottom, Ck indicates a waveform of asystem clock, AD[15:0] indicates the multiplex transfer operation ofaddress and data in address A0/data D0 to A15/D15 in the terminal numberof 6 to 21 shown in FIG. 12, /CS indicates the operation of the chipselect bar in the terminal number of 5 also shown in FIG. 12, /RDindicates the operation of the read bar in the terminal number of 4 alsoshown in FIG. 12, A[23:16] indicates an address output of address A16 toA23 in the terminal number of 22 to 29 shown in FIG. 12, and t0 to t13at the bottom each indicate a time synchronizing with a falling edge ofthe system clock Ck.

[0112] In order to read data from the ROM 42, the random access andsequential access can be switched as appropriate. In detail, in responseto the address data outputted from the second CPU core 362 a, themultiplex bus controller 362 c in the second game machine 30 outputs the/CS signal with the first timing (e.g., times t1 and t9), and also theaddress data to both the buses A[23:16] and AD[15:0]. At the fallingedge of the /CS signal, the address counter 441 loads (or latches) theupper address data provided by the bus A[23:16] and the lower addressdata provided by the bus AD[15:0]. A count value is then outputted tothe ROM 42 as the reading address data A0 to A23 (MA[23:0]). Thereafter,the multiplex bus controller 362 c outputs the /RD signal with thesecond timing (e.g., time t3). At the falling edge of the /RD signal,the multiaccess control part 44 outputs the data D0 to D15 (MD[15:0])read from the ROM 42 to the terminals 46-6 to 46-21. Thus outputted dataD0 to D15 is forwarded to the 32-bit circuit 362 via the I/O buffercontroller 363 of the second game machine 30.

[0113] In the address counter 441, every time the /RD signal comes intothe CLOCK terminal, the count value is incremented. In this manner, thesequential access control can be realized.

[0114] As such, the ROM 42 is subjected to random access control duringtimes t1 to t4, to sequential access control during times t5 to t8, andto random access control again during times t9 to t12. That means,during times t1 to t8, the /CS signal is set to low. In the meantime,the /RD signal is intermittently set to low during times t3 to t4, timest5 to t6, and times t7 to t8. Under such condition, a reading address isfirst outputted to AD[0:15] from before time t1 to after time t2, andthen data is sequentially accessed before time t4 to before time t9 sothat the data is sequentially read over three blocks. After before timet9, the random-access control is made.

[0115] Here, the sequential access is applied when addresses aresequentially read for contents of memory. Thus, when the addresses aresequential, the CPU has no need to output any address, and accordinglymemory address can be counted up only by using a control signal (/RD).That is, data can be read faster by the time supposedly taken foroutputting addresses. Alternatively, program data may be sequentiallyread in advance so as to smoothly activate the program.

[0116] The random access is applied when addresses are non-sequentiallyread for contents of memory. Therewith, an address is input every timememory is read, and thus reading data takes time.

[0117] As such, in the IC 48, the reason why the random access controland the sequential control are both applied (multiplex system) is asfollows. In detail, a multiplexed bus has an advantage in less number ofterminals (pins) for an interface bus, and some connection terminals areused as a common bus for both the address and data. Therefore, dataoutput cannot be done without address input, and consequently accessspeed takes longer than the normal bus. This problem can be tackled ifthe above-described sequential access control is applied. To carry outthe sequential access control, however, a memory side is provided with aspecial circuit (address counter) corresponding to the sequentialaccess.

[0118] On the other hand, writing/reading to/from the RAM 43, or readingfrom the ROM 22 can be realized by the random access. Time charts forthe operation as such are shown in FIGS. 15(b)-15(d). In such case, dataaccess is made separately through the address bus and the data bus, andthus the normal access system is applied instead of the multiplexsystem.

[0119] With reference to FIG. 16, described next is the operation of thepresent game system (especially, the second game machine 30). FIG. 16 isa flowchart showing the specific operation of the game system. To playthe game, first of all, the user inserts either the first or the secondgame cartridge 20 or 40 into the concave part 34 of the second gamemachine 30 for connection with the connector 37 (step S1). Then, in stepS2, the user turns on the power-supply switch 382, and then thefollowing processing is carried out.

[0120] In step S3, the detection switch 35 identifies, based on thestate of the selector 35 s, whether the inserted cartridge is the firstor the second game cartridge 20 or 40.

[0121] If the inserted cartridge is identified as being the second gamecartridge 40, the procedure goes to step S4, and processing for suchcase is executed. In detail, in step S4, as the selector 35 s remainsOFF and is connected to the 3.3V output terminal in the DC-DC converter383, the power-supply voltage of 3.3V is supplied to the secondcartridge 40. The procedure then goes to step S5.

[0122] In step S5, the register 362 f is loaded with a logical value “1”(high level) indicating the second game cartridge 40 is the onecurrently engaged. Then, the procedure goes to step S6.

[0123] In step S6, the reset circuit 385 resets and activates the CPU360. Then, the procedure goes to step S7.

[0124] In step S7, the 32-bit circuit 362 in the second game machine 30is activated, and in response, the second CPU core 362 a carries out anactivation program stored in the second boot ROM 362 e. The procedurethen goes to step S8.

[0125] In step S8, the second CPU core 362 a determines whether thevalue stored in the register 362 f is “1” or not. If Yes, the proceduregoes to step S9.

[0126] In step S9, the processing based on the program in the secondboot ROM 362 e is continuously executed. Then, the procedure goes tostep S10.

[0127] In step S10, the access control part 362 b starts its operation,and the ROM 42 in the second game cartridge 40 is controlled for reading(the RAM 43 is controlled for reading/writing, if required). Here, asdescribed above, the ROM 42 is controlled under the multiplex system. Inother words, with one access, the address data A0 to A15 (lower address)and A16 to A24 (upper address) are generated with the first timing, andforwarded to the ROM 42 via the terminals 46-6 to 46-29. And with thesecond timing, the data D0 to D15 is read through the terminals 46-6 to46-21. In this manner, the terminals 46-6 to 46-21 are used with bothtimings. Such bus switching is performed by the multiaccess control part44. Here, in case of the RAM 43 controlled for writing/reading, theterminals are not used with both timings, and thus the normal accesscontrol is applied instead of the multiplex system. Then, the proceduregoes to step S11.

[0128] In step S11, the second CPU core 362 a executes the game programfor the second game machine 30 read from the ROM 42, and then generatesa game image for display on the liquid crystal display 32. Also, thesound effects of the game are outputted to the speaker 392. Theprocedure then goes to step S12.

[0129] In step S12, it is determined whether the game is over. If not,the procedure returns to step S10, and repeats steps S10 and S11 untilthe game is through.

[0130] On the other hand, when the cartridge inserted into the secondgame machine 30 is the first game cartridge 20, the detection switch 35determines that the cartridge has no groove 412 in step S3. Theprocedure then goes to step S21.

[0131] In step S21, the processing for the first game cartridge 20 iscarried out. To be specific, as the selector 35 s is ON and is connectedto the 5V output terminal in the DC-DC converter 383, the power-supplyvoltage of 5V is provided to the first game cartridge 20. Then, theprocedure goes to step S22.

[0132] In step S22, the register 362 f is loaded with a logical value“0” (low level) indicating the first game cartridge 20 is the onecurrently engaged. Then, the procedure goes to steps S6 S7, and S8, andthen to step S23.

[0133] In step S23, the switching circuit 369 is started up, and then32-bit circuit 362 is switched to the 8-bit circuit 361. Then, theprocedure goes to step S24.

[0134] In step S24, the second CPU core 362 a is stopped, and the firstCPU core 361 a is activated. The procedure goes to step S25.

[0135] In step S25, the first CPU core 361 a executes an activationprogram stored in the first boot ROM 361 c. The procedure goes to stepS26.

[0136] In step S26, the 8-bit bus controller 361 b controls the ROM 22in the first game cartridge 20 for reading. In this case, the addressdata for processing of the first CPU core 361 a is generated with suchtiming as shown in FIG. 15(d). The procedure then goes to step S27.

[0137] In step S27, based on the game program for an 8-bit game machineread from the ROM 22 in the first game cartridge 20, the game processingfor the first game machine is executed. The procedure goes to step S28.

[0138] In step S28, it is then determined whether the game is now over.If not, the procedure returns to step S26, and repeats steps S26 and S27until the game is through.

[0139] Hereinafter, by referring to FIGS. 17, 18, 19, and 20, someexamples of the cartridge discrimination means other than the above aredescribed.

[0140] By referring to FIGS. 17 and 18, described first is an example ofdiscriminating the cartridge between the second game cartridge 40 andthe first game cartridge 20 by storing an identification code eachcorresponding to the cartridge type in a storage device provided in thecartridge, so that the identification code is read when power is turnedon.

[0141]FIG. 17 is, as is FIG. 7, a block diagram showing main partsrelevant to the above processing of discriminating the cartridge betweenthe first and second game cartridges 20 and 40. A second game machine 30r in this example is, compared with the second game machine 30 of FIG.7, provided with a voltage selector 38 instead of the detection switch35. Also the second game cartridge 40 is replaced with a second gamecartridge 40 r therein. Further, the voltage detector 384 and theregister 362 f provided in the second game machine 30 are not provided.The voltage selector 38 is connected to the 32-bit circuit 362, and iscontrolled by a control signal outputted therefrom.

[0142] In the second game cartridge 40 r, instead of the groove 412, theidentification code representing its type is stored in an identificationcode region 421 provided in the 3.3V interface memories 42 and 43. As isthe detection switch 35, the voltage selector 38 is a switch forselecting an output from the DC-DC converter 383, but operates notmechanically but electronically. With such structure change, in thisexample, the voltage detector 384 and the register 362 f shown in FIG. 7are not necessary any more. Thus, for the purpose of discriminating fromthe CPU 360 and the second game machine 30 of FIG. 7, suchdifferently-structured CPU and the information processing device arereferred to as CPU 360 r and second game machine 30 r, respectively.

[0143] Described next is the operation for cartridge discriminationutilizing the identification code in the above-described second gamemachine 30 r. When the second game machine 30 r is turned on, thevoltage of 3.3V goes to the first or second game cartridge 20 or 40.Then, the second CPU core 362 a is activated.

[0144] The second CPU core 362 a works to read the identification codestored in a specific region in memories provided in the first and secondgame cartridges 20 and 40. If successfully read and if the readidentification code indicates the second game cartridge 40 r, the secondCPU core 362 a keeps working.

[0145] If the read identification code does not indicate the second gamecartridge 40 r, or if failed to read the identification code, the secondCPU core 362 a identifies the cartridge as being the first gamecartridge 20. In this case, the 32-bit circuit 326 let the voltageselector 38 select 5V. The second CPU core 362 a then starts theswitching circuit 369.

[0146] The switching circuit 369 stops the second CPU core 362 a, andstarts the first CPU core 361 a.

[0147] Next, by referring to a flowchart shown in FIG. 18, the operationof the second game machine 30 r in this example is described. In thisflowchart, compared with the flowchart shown in FIG. 16, steps S3, S5,S6, S21, and S22 are not included, step S116 is included instead of stepS7, step S118 is included instead of step S8, and step S120 isadditionally included between steps S118 and S23.

[0148] Hereinafter, the operation of the second game machine 30 r isdescribed focusing on the steps unique to this example. First, in stepS1, the first game cartridge 20 or the second game cartridge 40 isinserted into the concave part 34 in the second game machine 30 r. Then,a user turns on the power-supply switch 382 in the second game machine30 r.

[0149] In step S4, the DC-DC converter 383 supplies, via the voltageselector 38, DC of 3.3V to the cartridge. The procedure then goes tostep S116.

[0150] In step S16, the second CPU core 362 a in the CPU 360 r isactivated, starts executing the processing described in the second bootROM 362 e, and then reads the identification code stored in theidentification code region in the inserted cartridge. Specifically, whenthe connector 37 is engaged with the second game cartridge 40 r, theidentification code is read from the identification code region 421.

[0151] On the other hand, when the connector 37 is engaged with thefirst game cartridge 20, as already described, the identification codeindicating the second game cartridge 40 r is not read. Then, theprocedure goes to step S118.

[0152] In step S118, based on the identification code read in step S116,the type of cartridge engaged with the connector 37 is determined. Inthis example, the cartridge being engaged is determined whether thesecond game cartridge 40 r or not.

[0153] If the engaged cartridge is determined as being the second gamecartridge 40 r, the procedure goes to steps S9 to S12, which aredescribed in the foregoing.

[0154] If the engaged cartridge is determined as not being the secondgame cartridge 40 r but the first game cartridge 20, the procedure goesto step S120.

[0155] In step S120, the voltage selector 38 selects 5V instead of 3.3V.Then, the procedure goes to steps S23 to S28, which are described in theforegoing.

[0156] Here, the processing in steps S116 and S118 is described in moredetail. In the case that the second game cartridge 40 r is engaged, theprocessing is carried out as already described. When the first gamecartridge 20 is engaged, however, normal access cannot be achieved withrespect thereto in step S116. This is because the voltage suppliedthereto in step S4 is 3.3V. Even if successfully accessed, the firstgame cartridge 20 has no identification code region 421. As a result, instep S116, the identification code indicating the first game cartridge20 is not read out, and thus it is determined as having the first gamecartridge 20 engaged, that is, determined as No.

[0157] Here, the second game cartridge 40 r and the first game cartridge20 may be driven by the same level of voltage (e.g., 3.3V), and are eachprovided with memory which is accessible by common bus control (e.g.,separate bus control) so as to store the identification code only. Ifso, the second CPU core 362 a becomes accessible to the memoryregardless of the cartridge type, and can correctly read theidentification code from the identification code region 421 or anidentification code region for the first game cartridge 20.

[0158] Next, by referring to FIGS. 19 and 20, a method is described foridentifying the type of cartridge utilizing a signal-line short. FIG. 19is, as is FIG. 17, a block diagram showing main parts relevant toprocessing of discriminating between the first and second cartridges 20and 40.

[0159] A second game machine 30 rr in this example is, compared with thesecond game machine 30 shown in FIG. 7, provided with the voltageselector 38 instead of the detection switch 35. Also the second gamecartridge 40 is replaced with a second game cartridge 40 rr therein.Further, the concave part 34 therein is additionally provided with twosignal lines W extending from the voltage selector 38. The second gamecartridge 40 rr is provided with a short S which causes those two signallines W to short out when the second game cartridge 40 rr is insertedinto the concave part 34.

[0160] In a so-structured second game machine 30 rr, the signal lines Ware not shorted when the first game cartridge 20 is the one insertedinto the concave part 34. However, when the second game cartridge 40 rris inserted into the concave part 34, those two signal lines W areshorted by the short S. Such short observed for those two signal lines Whelps the second game machine 30 rr identify the cartridge type throughdetection. Here, based on such short observed for those signal lines W,the voltage selector 38 selects either 3.3V or 5V.

[0161] The operation of the second game machine 30 rr for identifyingthe cartridge type based on the short observed for the two signal linesW is similar to that for the second game machine 30 r for identifyingthe cartridge utilizing the identification code. Note that, in thesecond game machine 30 rr, the second CPU core 362 a detects the shortobserved for the signal lines instead of reading the identificationcode. Since detected herein is only the short, it is possible tocorrectly detect the short even when the voltage supplied is 3.3Vresponding to the first game cartridge 20 engaged.

[0162] Next, by referring to the flowchart shown in FIG. 20, theoperation of the second game machine 30 rr is described. Compared withthe flowchart shown in FIG. 16, this flowchart does not have step S3,but is additionally provided with step S104 between step S2 and step S4or step S21.

[0163] Hereinafter, the operation of the second game machine 30 rr isdescribed focusing on the steps unique to this example. First, in stepS1, the cartridge is inserted into the concave part 34 in the secondgame machine 30 rr. In step S2, a user turns on the power-supply switch382 in the second game machine 30 rr.

[0164] In step S104, it is determined whether the signal lines W areshorted. If the signal lines W are determined to be shorted by the shortS provided in the second game cartridge 40 rr, the processing in theabove-described steps S4 to S12 is executed.

[0165] If the signal lines W are determined not to be shorted since thefirst game cartridge 20 has no short S, the processing in theabove-described steps S21 to S28 is executed.

[0166] As described in the foregoing, the first game cartridge 20 forthe first game machine 10 being a low-end machine is usable also for thesecond game machine 30 being a high-end machine. Thus, compatibilityamong the game cartridges (game soft) can be ensured. Further, dependingon the cartridge type currently engaged to a game machine, voltageswitch is automatically done and thus access control can be achieved.

[0167] Further, even if the level of the voltage supplied to a cartridgeand an access manner thereto vary depending on the memory type therein,the memory in the cartridge is accessible by identifying the cartridge,and according to the result obtained thereby, by switching the voltagelevel and an operation mode of central processing means.

[0168] When an information processing device or a game device, forexample, is provided with a professor in which the number of bits fordata processing is rather large, data width of a connector may not bewide enough. However, memory which has the number of data bitscorresponding to the number of bits in the processor for data processingcan be connected to a common bus. Further, when the informationprocessing device or game device, for example, is provided withprocessors each having the different number of bits for data processingto retain compatibility of software, for example, memories eachcorresponding to those processors are connected to the common bus to beaccessed.

[0169] Still further, a multiplex bus transfer mode technology isapplied to deal with not only two types of memories differed in numberof bits of an address signal but those differed in the number of bits ofa data signal. Also, a memory can be provided in which is stored in acartridge having a function used for cartridge discrimination betweenthe one for the second game machine 30 and the one for the informationprocessing system CGB.

[0170] While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

1. An information processing device which is detachably connectable to different peripheral devices each using a different data width, wherein at least one of the peripheral devices is provided with a characteristic for distinguishing that peripheral device from other peripheral devices, the information processing device comprising: a detecting circuit for detecting, based on the characteristic, which of the peripheral devices is connected to the information processing device; a processor for sending and/or receiving data via a data bus to/from the connected peripheral device; and bus control circuitry for selectively controlling the data bus in accordance with one of a plurality of different bus control modes based on which of the peripheral devices is detected by the detecting circuit.
 2. An information processing device as described in claim 1, wherein the different peripheral devices include at least two different memory devices.
 3. An information processing device as described in claim 2, wherein each of the at least two different devices includes a memory storing a game program.
 4. An information processing device as described in claim 1, wherein the detecting circuit comprises a shape detecting circuit.
 5. An information processing device as described in claim 1, wherein the information processing device comprises a game machine.
 6. An information processing device as described in claim 1, wherein the information processing device comprises a hand-held game machine.
 7. An information processing device as described in claim 1, wherein the plurality of bus control modes comprise a normal bus transfer mode and a multiplex bus transfer mode.
 8. A peripheral device detachably connectable with an information processing device via a connector to a bus having a first data width, the peripheral device comprising: an electrical component which uses a second data width wider than said first data width; and a multiplex bus conversion circuit for controlling, in a time-sharing manner, address and data exchange between the bus of the information processing device having the first data width and the electrical component using the second data width.
 9. A peripheral device as described in claim 8, wherein the multiplex bus conversion circuit comprises an address counter.
 10. A peripheral device as described in claim 8, wherein the electrical component comprises a general purpose memory.
 11. A peripheral device according to claim 8, wherein the multiplex bus conversion circuit comprises: an address storing circuit for storing an address value supplied from the information processing device via the bus; and an increment circuit for periodically incrementing the address value stored in the address storing circuit in response to a control signal supplied from the information processing device via the bus.
 12. A memory device detachably connectable with a game machine via a connector to a bus having a first data width, the memory device comprising: a first memory which uses a second data width wider than said first data width; and a multiplex bus conversion circuit for controlling, in a time-sharing manner, address and data exchange between the bus of the information processing device having the first data width and the first memory using the second data width.
 13. A memory device as described in claim 12, further comprising: a second memory which uses the first data width.
 14. A peripheral device according to claim 12, wherein the multiplex bus conversion circuit comprises: an address storing circuit for storing an address value supplied from the game machine via the bus; and an increment circuit for periodically incrementing the address value stored in the address storing circuit in response to a control signal supplied from the game machine via the bus.
 15. A memory access method for a hand-held display system for playing video games which includes user controls, a liquid crystal display and a processor, the method comprising: accessing by the processor a first portion of a memory which stores data having a first data width using a multiplex memory accessing scheme; and accessing by the processor of a second portion of the memory which stores data having a second data width using a non-multiplex accessing scheme.
 16. The memory access method according to claim 15, wherein the first portion of the memory comprises a read-only memory portion and the second portion of the memory comprises a read/write memory portion.
 17. The memory access method according to claim 16, wherein the read-only memory portion stores a video game program.
 18. The memory access method according to claim 15, wherein the first portion of the memory comprises a read-only portion addressable using addresses in an address range from 08000000h to 0DFFFFFFh and the second portion of the memory comprises a read/write portion addressable using addresses in an address range from 0E000000h to 0E00FFFFh.
 19. The memory access method according to claim 15, wherein the first portion of the memory comprises a 16-bit memory portion that is addressable using a 24-bit address and the second portion of the memory comprises an 8-bit memory that is addressable using a 16-bit address.
 20. The memory access method according to claim 15, wherein the multiplex memory accessing scheme selectively provides for sequential access and random access of the first portion of the memory.
 21. A bus control method for a hand-held display system for playing video games which includes user controls, a liquid crystal display and a processor, the method comprising: controlling a bus using a multiplex bus control method when accessing a first portion of a memory which stores data having a first data width; and controlling a bus using a non-multiplex bus control method when accessing a second portion of the memory which stores data having a second data width.
 22. A hand-held display system for playing video games, comprising: user controls; a display; and a processor for accessing a first portion of a memory which stores data having a first data width using a multiplex memory accessing scheme and for accessing a second portion of the memory which stores data having a second data width using a non-multiplex accessing scheme.
 23. The hand-held display system according to claim 22, wherein the first portion of the memory comprises a read-only memory portion and the second portion of the memory comprises a read/write memory portion.
 24. The hand-held display system according to claim 23, wherein the read-only memory portion stores a video game program.
 25. The hand-held display system according to claim 22, wherein the first portion of the memory comprises a read-only portion addressable using addresses in an address range from 08000000h to 0DFFFFFFh and the second portion of the memory comprises a read/write portion addressable using addresses in an address range from 0E000000h to 0E00FFFFh.
 26. The hand-held display system according to claim 22, wherein the first portion of the memory comprises a 16-bit memory portion that is addressable using a 24-bit address and the second portion of the memory comprises an 8-bit memory that is addressable using a 16-bit address.
 27. The hand-held display system according to claim 22, wherein the multiplex memory accessing scheme selectively provides for sequential access and random access of the first portion of the memory. 